Diamond Semiconductor System and Method

ABSTRACT

Disclosed herein is a new and improved system and method for fabricating monolithically integrated diamond semiconductor. The method may include the steps of seeding the surface of a substrate material, forming a diamond layer upon the surface of the substrate material; and forming a semiconductor layer within the diamond layer, wherein the diamond semiconductor of the semiconductor layer has n-type donor atoms and a diamond lattice, wherein the donor atoms contribute conduction electrons with mobility greater than 770 cm 2 /Vs to the diamond lattice at 100 kPa and 300K, and wherein the n-type donor atoms are introduced to the lattice through ion tracks.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the benefit of U.S. Provisional Application No.61/583,841, filed Jan. 6, 2012; and is a continuation of U.S.application Ser. No. 13/734,986, filed Jan. 6, 2013.

BACKGROUND

1. Field

This invention is generally related to semiconductor fabricationmethods, and more particularly to a method for fabricating diamondsemiconductors.

2. Background

Diamond possesses favorable theoretical semiconductor performancecharacteristics. However, practical diamond based semiconductor deviceapplications remain limited. One issue that has limited the developmentof practical diamond based semiconductors is the difficulty offabricating quality n-type layers in diamonds. While attempts have beenmade to improve n-type diamond fabrication based on limiting theconcentration of vacancy created defects, the difficulties associatedwith fabricating quality n-type layers in diamond has yet to besufficiently resolved. Deficiencies in known diamond fabricationtechnology include those related to formation of high power circuitelements for monolithic system level integration. Therefore, there is aneed for a new and improved system and method for fabricating diamondsemiconductors, including n-type layers within diamond semiconductorsfor high power circuit elements for monolithic system level integration.

SUMMARY

Disclosed herein is a new and improved system and method for fabricatingdiamond semiconductors. In accordance with one aspect of the approach, amethod of fabricating monolithically integrated diamond semiconductor.The method may include the steps of seeding the surface of a substratematerial, forming a diamond layer upon the surface of the substratematerial; and forming a semiconductor layer within the diamond layer,wherein the diamond semiconductor of the semiconductor layer has n-typedonor atoms and a diamond lattice, wherein at least 0.16% of the donoratoms contribute conduction electrons with mobility greater than 770cm²/Vs to the diamond lattice at 100 kPa and 300K.

Other systems, methods, aspects, features, embodiments and advantages ofthe system and method for fabricating diamond semiconductors disclosedherein will be, or will become, apparent to one having ordinary skill inthe art upon examination of the following drawings and detaileddescription. It is intended that all such additional systems, methods,aspects, features, embodiments and advantages be included within thisdescription, and be within the scope of the accompanying claims.

BRIEF DESCRIPTION OF THE DRAWINGS

It is to be understood that the drawings are solely for purpose ofillustration. Furthermore, the components in the figures are notnecessarily to scale, emphasis instead being placed upon illustratingthe principles of the system disclosed herein. In the figures, likereference numerals designate corresponding parts throughout thedifferent views.

FIG. 1 is a block diagram of a first embodiment of the method forfabricating diamond semiconductors.

FIG. 2A is a perspective view of a prior art model of an intrinsicdiamond thin film wafer upon which the method of FIG. 1 may bepracticed.

FIG. 2B is a prior art model of an intrinsic diamond lattice structureof the diamond of FIG. 2A.

FIG. 3A is a perspective view of an exemplary model of a doped diamondthin film wafer such as may be fabricated by practicing the method ofFIG. 1 upon the intrinsic diamond thin film wafer of FIG. 2.

FIG. 3B is a model of a doped diamond lattice structure of the dopeddiamond thin film wafer of FIG. 3A.

FIG. 4 is a block diagram of a second embodiment of the method forfabricating diamond semiconductors.

FIG. 5A and FIG. 5B are a block diagram of a third embodiment of themethod for fabricating diamond semiconductors.

FIG. 6 is a top view of an exemplary P⁺-i-N diode model that may befabricated according to the method of FIG. 5A and FIG. 5B.

FIG. 7 is a perspective view of a model of an exemplary six-pin surfacemount device package that may be fabricated according to the method ofFIG. 5A and FIG. 5B.

FIG. 8 shows a schematic diagram of a diode test condition setup, suchas may be employed with the diode model of FIG. 6.

FIG. 9 is a graphical illustration of the threshold voltage performancecharacteristics of a diode that may be fabricated according to themethod of FIG. 5A and FIG. 5B.

FIG. 10 shows a block diagram of an embodiment of a method for formingOhmic contacts to diamond material.

FIG. 11 shows a block diagram of an embodiment of a method for formingSchottky type contacts to diamond material.

FIG. 12 is a block diagram of a method for forming monolithicallyintegrated circuits from diamond semiconductor materials.

FIG. 13 is a perspective view of a model of a doped diamond thin filmwafer, such as may be fabricated by according to the method of FIG. 12.

FIG. 14 is a schematic diagram of a P⁺-i-N diode device that may befabricated according to the method of FIG. 12.

FIG. 15 is a block diagram of a method for forming monolithicallyintegrated circuit devices from diamond semiconductor materials.

FIG. 16 is a schematic diagram of a NAND logic gate that may be formedby the methods disclosed.

FIG. 17 is a block diagram of a method for forming a transistor elementfrom diamond semiconductor materials.

FIG. 18 is a model of a transistor that may be fabricated according tothe method of FIG. 17.

DETAILED DESCRIPTION

The following detailed description, which references to and incorporatesthe drawings, describes and illustrates one or more specificembodiments. These embodiments, offered not to limit but only toexemplify and teach, are shown and described in sufficient detail toenable those skilled in the art to practice what is claimed. Thus, forthe sake of brevity, the description may omit certain information knownto those of skill in the art.

FIG. 1 shows a block diagram of a first embodiment of the method 100 forfabricating layers within diamond material. The method 100 may include afirst step 102 of selecting a diamond material having a diamond latticestructure. The diamond material is intrinsic diamond. Intrinsic diamondis diamond that has not been intentionally doped. Doping may introduceimpurities for the purpose of giving the diamond material electricalcharacteristics, such as, but not limited to, n-type characteristics andp-type characteristics. The diamond material may be a single crystal orpolycrystalline diamond.

FIG. 2A is a perspective view of a model of an intrinsic diamond thinfilm wafer 200. Though not limited to any particular diamond material,in one embodiment, the diamond material of method 100 is the intrinsicdiamond thin film wafer 200. The intrinsic diamond thin film wafer 200may include a diamond layer 202, a silicon dioxide layer (SiO₂) 204, anda silicon wafer layer 206. Diamond layer 202 may be, but is not limitedto, ultrananocrystalline diamond. The intrinsic diamond thin film wafer200 may be 100 mm in diameter. The diamond layer 202 may be a 1 μmpolycrystalline diamond having a grain size of approximately 200-300 nm.The silicon dioxide layer (SiO₂) 204 may be approximately 1 μm. Thesilicon wafer layer 206 may be approximately 500 μm Si, such as Aqua 100available from Advanced Diamond Technologies, Inc. The first step 102 ofmethod 100 may include selecting a variety of diamond base materialssuch as, but not limited to, the exemplary diamond layer 202 ofintrinsic diamond thin film wafer 200.

FIG. 2B is a model of an intrinsic diamond lattice structure 210, suchas, but not limited to, an intrinsic diamond lattice structure ofdiamond layer 202. The intrinsic diamond lattice structure 210 mayinclude a plurality of carbon atoms 212. The intrinsic diamond latticestructure 210 is known to those having skill in the art. In the model,the intrinsic diamond lattice structure 210 is shown defect free and allof the atoms shown are carbon atoms 212.

The second step 104 of method 100 may include introducing a minimalamount of acceptor dopant atoms to the diamond lattice to create iontracks. The creation of the ion tracks may include creation of anon-critical concentration of vacancies, for example, less than 10²²/cm³for single crystal bulk volume, and a diminution of the resistivepressure capability of the diamond layer 202. For example, second step104 may include introducing the acceptor dopant atoms using ionimplantation at approximately 293 to 298 degrees Kelvin (K) in a lowconcentration. The acceptor dopant atoms may be p-type acceptor dopantatoms. The p-type dopant may be, but is not limited to, boron, hydrogenand lithium. The minimal amount of acceptor dopant atoms may be suchthat carbon dangling bonds will interact with the acceptor dopant atoms,but an acceptor level is not formed in the diamond lattice.

The minimal amount of acceptor dopant atoms of second step 104 may befor example, but is not limited to, approximately 1×10¹⁰/cm³ of boron.In other embodiments, the minimal amount of acceptor dopant atoms ofsecond step 104 may be for example, but is not limited to, approximately5×10¹⁰/cm³ of boron and a range of 1×10⁸/cm³ to 5×10¹⁰/cm³. Second step104 may be accomplished by boron co-doping at room temperature in thatcreated vacancies may be mobile, but boron may take interstitialpositioning. The second step 104 may create mobile vacancies forsubsequent dopants, in addition to some substitutional positioning.

The ion tracks of second step 104 may be viewed as a ballistic pathwayfor introduction of larger substitutional dopant atoms (see third step106 below). Second step 104 may also eliminate the repulsive force (withrespect to the substitutional dopant atoms (see step 106 below)) of thecarbon dangling bonds in the diamond lattice by energetically favoringinterstitial positioning of the acceptor dopant atoms, and altering thelocal formation energy dynamics of the diamond lattice.

The third step 106 of method 100 may include introducing thesubstitutional dopant atoms to the diamond lattice through the iontracks. For example, third step 106 may include introducing the largersubstitutional dopant atoms using ion implantation preferably at orbelow approximately 78 degrees K for energy implantation at less than500 keV. Implanting below 78 degrees K may allow for the freezing ofvacancies and interstitials in the diamond lattice, while maximizingsubstitutional implantation for the substitutional dopant atoms. Thelarger substitutional dopant atoms may be for example, but is notlimited to, phosphorous, nitrogen, sulfur and oxygen.

For implantation where the desired ion energy is higher, as localself-annealing may occur, it may be beneficial to use ambienttemperature in conjunction with MeV energy implantation. Where thedesired ion energy is higher, there may be a higher probability of anincoming ion taking substitutional positioning.

The larger substitutional dopant atoms may be introduced at a muchhigher concentration than the acceptor dopant atoms. The higherconcentration of the larger substitutional dopant atoms may be, but isnot limited to, approximately 9.9×10¹⁷/cm³ of phosphorous and a range of8×10¹⁷ to 2×10¹⁸/cm³.

In third step 106, the existence of the ballistic pathway andminimization of negative repulsive forces acting on the substitutionaldopant atoms facilitates the entry of the substitutional dopant atomsinto the diamond lattice with minimal additional lattice distortion. Ionimplantation of the substitutional dopant atoms at or belowapproximately 78 degrees K provides better impurity positioning,favoring substitutional positioning over interstitial positioning, andalso serves to minimize the diamond lattice distortions because fewervacancies are created per impinging ion.

In one embodiment, ion implantation of step 106 may be performed at 140keV, at a 6 degree offset to minimize channeling. Implant beam energymay be such that dosages overlap in an active implant area approximately25 nm below the surface so that graphitic lattice relaxation isenergetically unfavorable. Doping may be performed on a Varian IonImplantation System with a phosphorus mass 31 singly ionized dopant(i.e., 31P+); a beam current of 0.8 μA; a beam energy of 140 keV; a beamdose 9.4×10¹¹/cm²; an incident angle of 6 degrees; and at a temperatureof at or below approximately 78 degrees K.

The fourth step 108 of method 100 may include subjecting the diamondlattice to rapid thermal annealing. The rapid thermal annealing may bedone at 1000 degree celsius C. Rapid thermal annealing may restoreportions of the diamond lattice that may have been damaged during thesecond step 104 and the third step 106 and may electrically activate theremaining dopant atoms that may not already be substitutionalypositioned. Higher temperatures at shorter time durations may be morebeneficial than low temperature, longer duration anneals, as the damagerecovery mechanism may shift during long anneal times at temperatures inexcess of 600 C.

FIG. 3A is a perspective view of a model of a doped diamond thin filmwafer 300, such as may be fabricated by subjecting the intrinsic diamondthin film wafer 200 to method 100. The doped diamond thin film wafer 300may include a doped diamond layer 302, the silicon dioxide layer (SiO₂)204, and the silicon wafer layer 206.

FIG. 3B is a model of a doped diamond lattice structure 304, such as maybe the result of subjecting the diamond layer 202 to method 100. Thedoped diamond lattice structure 304 may include a plurality of carbonatoms 314, a plurality of phosphorus atoms 306, and a plurality ofvacancies 308, and a boron atom 312.

The method 100 allows for the fabrication of a semiconductor systemincluding a diamond material, such as, but not limited to, the dopeddiamond thin film wafer 300, having n-type donor atoms, such as, but notlimited to, the plurality of phosphorus atoms 306, and a diamondlattice, such as, but not limited to, the doped diamond latticestructure 304, wherein, for example by way of shallow ionization energy,approximately 0.25 eV, 0.16% of the donor atoms contribute conductionelectrons with mobility greater than 770 cm2/Vs to the diamond latticeat 100 kPa and 300K.

FIG. 4 shows a block diagram of a second embodiment of the method 400for fabricating layers within diamond material. The first step of method400 may be the same as the first step 102 of method 100, which includesselecting a diamond material having a diamond lattice structure.

The second step 402 of method 400 may include cleaning the diamondmaterial to remove surface contaminants. For example, second step 402may include cleaning the intrinsic diamond thin film wafer 200 (see FIG.2). The cleaning may be a strong clean, for example but not limited to,a standard diffusion clean, known to those having skill in the art. Oneexample, of such a diffusion clean includes: applying a 4:1 solution ofH₂SO₄/H₂O₂ for 10 minutes; applying a solution of H₂O₂ for 2.5 minutes;applying a 5:1:1 solution of H₂O/H₂O₂/HCL for 10 minutes; applying asolution of H₂O₂ for 2.5 minutes; and heat spin drying for 5 minutes.

The third step 404 of method 400 may include subjecting the diamondmaterial to a pre-ion track mask deposition over a first portion of thediamond lattice. The pre-ion track mask may protect a first portion ofthe diamond material during ion implantation. The pre-ion track maskdeposition may be an aluminum pre-implant mask deposition. The pre-iontrack mask deposition may be performed using a Gryphon Metal SputterSystem using aluminum of 99.99999% (6N) purity, with a deposition timeof 21-24 seconds, at a power of 7.5 kW, a pressure: 2.5×10⁻³ Torr; andto a thickness of 30 nm.

The fourth step of method 400 may be the same as the second step 104 ofmethod 100, which includes introducing a minimal amount of acceptordopant atoms to the diamond lattice to create ion tracks.

The fifth step of method 400 may be the same as the third step 106 ofmethod 100, which includes introducing the substitutional dopant atomsto the diamond lattice through the ion tracks.

The sixth step 406 of method 400 may include mask etching, cleaning, andannealing the diamond lattice. The mask etching may be an aluminum masketch. The mask etching may be a wet etch using aluminum etchant, forexample, a Cyantek AL-11 Aluminum etchant mixture or an etchant having acomposition of 72% phosphoric acid; 3% acetic acid; 3% nitric acid; 12%water; and 10% surfactant, at a rate of 1 μm per minute. After thealuminum is removed visually, which may take approximately 30 seconds,the wafers may be run under de-ionized water for sixty seconds and driedvia pressurized air gun.

In other embodiments, the mask etching of the sixth step 406 may be ablanket etch using reactive ion etching (Ar(35 SCCM)/O₂ (10 SCCM), atV_(BIAS) 576 V, 250 W Power, under pressure of 50 mTorr, for a totaletch thickness of 25 nm. The Ar/O₂ etch may have a dual function of bothetching and polishing/terminating the diamond material surface. Inaddition to initial etching, the same process recipe is laterimplemented to form device architecture, and define different active andinactive areas of the diamond, as per required by end application use(i.e., MOSFET, diode, LED, etc.). Etch masking layer, for example a 200nm thick aluminum deposition, may be formed via standard E-beamevaporation. Etching may be performed on an Oxford System 100 PlasmalabEquipment (Oxford Deep Reactive Ion Etcher). The etching conditions maybe: RIE Power: 200 W; ICP power: 2000 W; Pressure: 9 mTorr; O₂ flow: 50sccm; Ar flow: 1 sccm. The etching rates may be 155 nm/min for thediamond layer and 34 nm/min for the aluminum masking layer.

The cleaning of sixth step 406 may be similar to diffusion cleandescribed in the second step 402. The annealing of sixth step 406 may bea rapid thermal annealing to approximately 1000-1150 degrees Celsiusunder flowing N₂ for approximately 5 minutes and/or the rapid thermalannealing may be performed with an Agilent RTA model AG4108 operatingunder the settings shown in Table 1.

TABLE 1 Command Time(s)/Intensity (%) Temperature Gas Flow Delay 20_sN/A 10 SLPM N₂  Delay  5 s N/A 7 SLPM N₂ Inin 8%  25° C. 4 SLPM N₂ Ramp10 s 650° C. 4 SLPM N₂ Steady 15 s 650° C. 4 SLPM N₂ Ramp 10 s 900° C. 4SLPM N₂ Steady 55 s 950° C. 4 SLPM N₂ Ramp 30 s 650° C. 7 SLPM N₂ Delay15 s N/A 7 SLPM N₂

The sixth step 406 of method 400 may include subjecting the diamondmaterial to a pre-substitutional mask deposition over a portion of thediamond lattice. The pre-substitutional mask deposition may be analuminum pre-implant mask deposition. The pre-substitutional maskdeposition may be performed using a Gryphon Metal Sputter System usingaluminum of 99.99999% (6N) purity, with a deposition time of 21-24seconds, at a power of 7.5 kW, a pressure: 2.5×10⁻³ Torr; and to athickness of 30 nm.

For some applications, it may be beneficial to differentially dopedifferent parts of the same diamond wafer, for example, to create p-typeand n-type regions. In embodiments, various semiconductor devices arecreated including P-N junctions and P-i-N junctions.

FIG. 5A and FIG. 5B show a block diagram of a third embodiment of themethod 500 for fabricating layers within diamond material. Method 500provides a process for fabricating n-type layers within diamondsemiconductors for a P⁺-i-N diode. The first step of method 500 may bethe same as the first step 102 of method 100, which includes selecting adiamond material having a diamond lattice structure.

FIG. 6 shows a top view of an exemplary model of a P⁺-i-N diode 600 thatmay be fabricated according to method 500. P⁺-i-N diode 600 may includea lightly doped semiconductor region (i) (for example, see FIG. 8, 804),between a p⁺-type semiconductor region 608, and an n-type semiconductorregion 606. The method of 500 with SRIM, Stopping and Range of Ions inMatter, modeling provides a path for fabricating P⁺-i-N diodes thatapproach theoretical projections. In one embodiment, the P⁺-i-N diode600 may include the lightly doped semiconductor region (i) 804 of adepth of approximately 10 nm, between a p-type semiconductor (forexample, see FIG. 8, 806) of a depth of approximately 150 nm, thep⁺-type semiconductor region 608 of a depth of approximately 100 nm, andthe n-type semiconductor region 606 of a depth of approximately 100 nm.FIG. 6 also shows a metallic contact/bonding pad 604 for connecting tothe p⁺-type semiconductor region 608.

The second step of method 500 may be the same as the second step 402 ofmethod 400, including cleaning the diamond material to remove surfacecontaminants.

The third step 502 of method 500 may include subjecting the diamondmaterial to a pre-P⁺ mask deposition over a non-P⁺ portion of thediamond lattice. The pre-P⁺ mask deposition may protect a non-P⁺ portionof the diamond material during P⁺ ion implantation. The pre-P⁺ maskdeposition may be an aluminum pre-implant mask deposition. The pre-iontrack mask deposition may be performed using a Gryphon Metal SputterSystem using aluminum of 99.99999% (6N) purity, with a deposition timeof 21-24 seconds, at a power of 7.5 kW, a pressure: 2.5×10⁻³ Torr; andto a thickness of 30 nm.

The fourth step 504 of method 500 may include a P⁺ layer implant of thediamond material. The P⁺ layer implant may be performed with a dopant of11B⁺, at a beam current of 0.04 μA, at a beam energy of 55 keV, with abeam dose of 1×10²⁰ atoms/cm², at an incident angle of 6 degrees, and ator below approximately 78 degrees K, to create a P⁺ layer of 100 nm.

The fifth step of method 500 may be the same as the sixth step 406 ofmethod 400, including mask etching, cleaning, and annealing the diamondmaterial.

The sixth step 506 of method 500 may include subjecting the diamondmaterial to a pre-P mask deposition over a non-P portion of the diamondlattice. The pre-P mask deposition may protect a non-P portion of thediamond material during P ion implantation. The pre-P mask depositionmay be an aluminum pre-implant mask deposition. The pre-P maskdeposition may be performed using a Gryphon Metal Sputter System usingaluminum of 99.99999% (6N) purity, with a deposition time of 21-24seconds, at a power of 7.5 kW, a pressure: 2.5×10⁻³ Torr; and to athickness of 30 nm.

The seventh step 508 of method 500 may include a P layer implant of thediamond material. The P layer implant may be performed with a dopant of11B+, at a beam current of 0.04 μA, at a beam energy of 55 keV, with abeam dose of 3×10¹⁷ atoms/cm², at an incident angle of 6 degrees, and ator below approximately 78 degrees K, to create a P layer of 150 nm.

The eighth step of method 500 may be the same as the sixth step 406 ofmethod 400, including mask etching, cleaning, and annealing the diamondmaterial.

The ninth step of method 500 may be the same as the third step 404 ofmethod 400, including subjecting the diamond material to a pre-ion trackmask deposition over a first portion of the diamond lattice.

The tenth step of method 500 may be the same as the second step 104 ofmethod 100, which includes introducing a minimal amount of acceptordopant atoms to the diamond lattice to create ion tracks.

The eleventh step of method 500 may be the same as the third step 106 ofmethod 100, which includes introducing substitutional dopant atoms tothe diamond lattice through the ion tracks.

The twelfth step of method 500 may be same as the sixth step 406 ofmethod 400, including mask etching, cleaning, and annealing the diamondmaterial.

The thirteenth step 510 of method 500 may include a blanket etch. Thethirteenth step 510 may include a blanket etch in which the surfacelayer, approximately 25 nm, of the diamond layer 202 is etched off toremove any surface graphitization.

The fourteenth step 512 of method 500 may include aphotolithography/mesa etch to obtain a diamond stack structure, such asthat shown in FIG. 6. The fourteenth step 512 may include a diffusionclean and photolithography prior to the mesa etch.

The fifteenth step 514 of method 500 may include a creating a contactfor the top of the stack. Contact to the top of the stack may beachieved by evaporating ITO with 5N purity to a thickness of 200 nm ontothe stack through a shadow mask and then performing a liftoff.

The sixteenth step 516 of method 500 may include annealing. Theannealing of step 516 may be oven annealing at 420 degrees C. in Arambient until ITO transparency is attained, which may be inapproximately 2.5 hours.

The seventeenth step 518 of method 500 may include creating Ohmiccontacts. The Ohmic contacts may include contacts to the P⁺ layer, forexample, the metallic contact/bonding pad 604, and the n-layer. As wirebonding may be difficult with a small contact area, Ti and Au layers maybe evaporated through a shadow mask using photolithography. Ti may alsofunction as a diffusion barrier between ITO and Au layers. A contactlayer thickness of 30 nm may be created for the P⁺ layer. A contactlayer thickness of 200 nm may be created for the N-layer. In oneembodiment, the diamond cap layer may be removed to expose the newlyformed n-type layer to form an electrical contact for device use. Thestep may include polishing the diamond layer while etching, thusminimizing the surface roughness, and electrically terminating (oxygen)the surface of the diamond, a step in semiconductor device fabrication.In some embodiments, there is a further step of forming metal contactson the diamond so that the diamond may function as a component part ofan electronic device. The seventeenth step 518 of method 500 may includea metal furnace annealing. The metal furnace annealing may be performedat 420 degrees celsius for two hours.

The eighteenth step 520 of method 500 may include wafer surfacetermination. The nineteenth step 522 of method 500 may include wafersurface dicing. The twentieth step 524 of method 500 may includepackaging. In the twentieth step 524, portions of the diamond materialmay be diced, mounted, wire bound and encapsulated in transparentsilicone sealant to create 6-pin surface mount device packages.

FIG. 7 shows a perspective view of a model of an exemplary six-pinsurface mount device package 700 that may be fabricated according to themethod of FIG. 5A and FIG. 5B.

The methods disclosed herein may allow for the creation of a number ofelectrical diamond junctions to serve functions traditionally served bysilicon semiconductors. While the application discusses examples in thecontext of a bipolar diode, those having skill in the art will recognizethat the present techniques describe novel genuine n-type diamondmaterial and novel p-type diamond material that may be used in multiplevariations of electrical devices and monolithically formed combinationsof the variations, including FETs and other switches, digital andanalog, and light emitting bodies, and are not limited to the specificimplementations shown herein. The various preferred embodiments need notnecessarily be separate from each other and can be combined.

FIG. 8 shows a schematic diagram of a P⁺-i-N diode test condition setup802. A P⁺-i-N diode, such as a P⁺-i-N diode 600 fabricated according tomethod 500, may be tested according to the P⁺-i-N diode test conditionsetup 802.

FIG. 9 shows a block diagram of an embodiment of a method 900 foretching diamond material. Impurities in the diamond layer 202 may effectthe uniformity, rate of the etching, and chemical reactivity. Inductivecoupled plasma RIE (ICP-RIE) may allow for polished diamond surfaceswith lithographic patterning required for semiconductor devices andelectronic isolation of exposed etched areas. ICP-RIE may result inreduced process time and reduce the complexity of the semiconductorprocess line.

The first step of method 900 may be the same as the first step 102 ofmethod 100, which includes selecting a diamond material having a diamondlattice structure. The second step of method 900 may be the same as thesecond step 402 of method 400, which includes cleaning the diamondmaterial to remove surface contaminants.

The third step 902 of method 900 may include mask deposition. The maskdeposition may include the application of a patterned or uniformlydeposited mask comprised of photoresist or metallic elements such as,but not limited to, aluminum. Aluminum may provide desirous propertiesas etch activity of the diamond material may be equal or better than 5.8times the aluminum layer.

The fourth step 904 of method 900 may include mask etching. Etching maybe performed on a number of systems, such as but not limited to Oxfordsystems. Etching may be performed using an Oxford System 100 PlasmalabEquipment (Oxford Deep Reactive Ion Etcher). The etching conditions maybe: RIE Power: 200 W; ICP power: 2000 W; Pressure: 9 mTorr; O₂ flow: 50sccm; Ar flow: 1 sccm. The etching rates may be 620 nm/min.

In other embodiments, for example embodiments that may be used forremoving diamond surface graphitization, such as carbon dangling bonds,etching conditions may be: RIE Power: 150 W and ICP power: 250 W, foretching rates of approximately 60 nm/min. The duration of the etch maybe confirmed by visual characterization of surface features throughoptical micrograph. In some embodiments, the etching duration fornanocrystalline and microcrystalline film may be 20 seconds.

FIG. 10 shows a block diagram of an embodiment of a method 1000 forforming Ohmic contacts to diamond material. The first step of method1000 may be the same as the first step 102 of method 100, which includesselecting a diamond material having a diamond lattice structure. In someembodiments, the diamond material may be formed upon a metal substrate,such as, but not limited to, tungsten. In some embodiments, the diamondmaterial of step 102 may include a diamond band gap. The second step ofmethod 1000 may be the same as the second step 402 of method 400, whichincludes cleaning the diamond material to remove surface contaminants.

The third step 1002 of method 1000 may include terminating the diamondsurface. Terminating the diamond surface may include electricallyisolating the diamond surface through methods such as, but not limitedto, hydrogen termination and oxygen termination, in order to pin thesurface states.

The fourth step 1004 of method 1000 may include creating a pattern onthe diamond surface. Creating a pattern on the diamond surface mayinclude lithography techniques such as but not limited to photoresistand other masking techniques.

The fifth step 1006 of method 1000 may include performing evaporationtechniques. Evaporation techniques may include forming circuit elementconfigurations by evaporating contact metals upon the diamond surface.

The contact metal selected may be based upon the relative band gappositioning or work function requirements. The metal may be selected tomaximize the operation of the desired device based upon a comparison ofthe relative Fermi positioning of the metal ahead of contact with thediamond surface, and the band structure of the proposed contact, such asfor Ohmic or Schottky contact. In some embodiments, the metal may becomprised of gold, silver, aluminum, palladium, copper, tungsten,titanium, and polysilicon. In some embodiments, the metal may atransparent metal, such as but not limited to, indium-tin-oxide andfluorine-tin-oxide. In the case of transparent metals alloyed withsingle metal gold, a titanium layer may be deposited before the goldlayer, where titanium may act as a diffusion barrier.

In some embodiments, such as those in requiring greater bond strength,such as wire bonding, performing evaporation techniques may includeapplying a metal carbide interfacial metal between the diamond surfaceand other contact metal, such as but not limited to, titanium, silicon,and tin.

The sixth step 1008 of method 1000 may include performing liftofftechniques. Liftoff techniques may include stripping the diamond surfaceof the masking material.

The seventh step 1010 of method 1000 may include annealing. Theannealing of step 1010 may be oven annealing at 350 degrees C. forgreater than 45 minutes per 300 nm thickness under flowing nitrogen gas.

FIG. 11 shows a block diagram of an embodiment of a method 1100 forforming Schottky type contacts to diamond material. The first step ofmethod 1100 may be the same as the first step 102 of method 100, whichincludes selecting a diamond material having a diamond latticestructure. The second step of method 1100 may be the same as the secondstep 402 of method 400, which includes cleaning the diamond material toremove surface contaminants. The third step of method 1100 may be thesame as the third step 1002 of method 1000, which includes terminatingthe diamond surface.

The fourth step 1102 of method 1100 may include masking the diamondsurface. Masking the diamond surface may include placing a shadow maskupon the diamond surface. In some embodiments, mask the diamond surfacemay be accomplished in the same manner as the fourth step 1004 of method1000.

The fifth step 1104 of method 1100 may include a vapor deposition ofmetal upon the diamond surface. The fifth step may be performed using asputtering tool known to those having skill in the art.

Additional embodiments of methods for forming contacts to diamondsurfaces may include degeneratively doping the diamond material wherethe band gap is minimized prior to application of the metal contact.Such alternative embodiments may provide for improved heat transfer andelectron transfer characteristics. Further embodiments may includeproviding a dielectric material interface layer to restrict currentflow.

The systems and fabrication methods described herein provide a number ofnew and useful technologies, including novel n-type and novel p-typediamond semiconducting materials and devices, and methods forfabricating novel n-type and novel p-type diamond semiconductingmaterials and devices.

The novel fabrication methods include, but are not limited to, those forcreating, etching, and metalizing (Schottky and Ohmic) genuine qualityn-type diamond material; creating Integrated Circuits (ICs) and devicedrivers from diamond based power elements.

The novel devices include, but are not limited to, n-type diamondsemiconductors that are at least partially activated at roomtemperature—i.e., the device material has sufficient carrierconcentration to activate and participate in conduction; n-type diamondwith high electron mobility; n-type diamond which has both high carriermobility and high carrier concentration—without requiring a hightemperature (above room temperature) or the presence of a highelectrical field; an n-type diamond semiconductor with an estimatedelectron mobility in excess of 1,000 cm²/Vs and a carrier concentrationof approximately 1×10¹⁶ electrons/cm³ at room/ambient temperature; abipolar diamond semiconductor device; devices with p-type and n-typeregions on a single diamond wafer; diamond diode devices; bipolardiamond semiconductor devices carrying high current withoutnecessitating either a high temperature or the presence of a strongelectrical field; bipolar diamond semiconductor devices which can carrya one milliamp current while at room temperature and in the presence ofa 0.28V electrical field; an n-type diamond material on polycrystallinediamond; a low cost thin film polycrystalline diamond-on-siliconcarrier; diamond semiconductors on other carrier types (e.g., FusedSilica, Quartz, Sapphire, Silicon Oxide or other Oxides, etc.); adiamond power RF attenuator, a polycrystalline diamond power RFattenuator chip, a polycrystalline diamond power RF attenuator device; adiamond light emitting diode or/laser diode (LED); monolithicallyintegrate diamond based logic drivers with high power elements (e.g.,LED) on the same chip; n-type diamond material which is stable in thepresence of oxygen (i.e., if a non-negligible amount of oxygen ispresent on the surface (such as when the wafer is on open air) then-type semiconductor's conductivity and performance continue).

In some embodiments, this n-type and novel p-type diamond semiconductingmaterial is constructed using polycrystalline diamond having less than amicrometer size grain and with doped thin film layers having sizes onthe order of less than 900 nm. The techniques for forming said diamondmaterial may be used on diamond films with diamond grain boundaries thatare nearly atomic abrupt, such that uniformity of electrical performancemay be maintained, while enabling the ability to form thin-film featuresfrom said material.

Another aspect of the invention is the ability to create metal contactsattached to the diamond semiconducting material, including the n-typematerial. Said metal contacts attach to the diamond material andcontinue to have good/ohmic conductivity (e.g., displaying highlinearity). Metal contacts may refer to either or both metals (e.g., Au,Ag, Al, Ti, Pd, Pt, etc.) or transparent metals (e.g., indium tin oxide,fluoride tin oxide, etc.), as warranted by desired application use.

FIG. 12 shows a block diagram of an embodiment of a method 1200 forforming monolithically integrated circuits from diamond semiconductormaterials. The method 1200 may include a first step 1202 of selecting asubstrate material. The substrate material of method 1200 may include,but is not limited to, silicon oxide materials, SiO₂, fused silica,quartz, sapphire, gallium nitride (GaN), gallium arsenide (GaAs), andrefractory metals. In addition, the substrate materials may includecarbon-carbon bonding allows integration with other materials such asSiC, Graphene, Carbon Nano Tubes (CNT), as well single crystal,polycrystalline diamond materials, and combinations of the materialsmentioned and other materials known to those having skill in the art.First step 1202 may form, for example, a substrate material layer 1306(See FIG. 13).

The method 1200 may include a second step 1204 of seeding a surface ofthe substrate material. The substrate material may be seeded with ananocrystalline diamond solution mixture. In one embodiment, the surfaceof the substrate may be ultrasonically roughened so as to facilitate auniform and strong cohesion of growth diamond material. The seeding ofthe substrate material surface of second step 1204 may help form, forexample and in part, a layer boundary 1308 (See FIG. 13).

The method 1200 may include a third step 1206 of forming a diamond layerupon the surface of the substrate material. The diamond layer may beformed by depositing diamond materials utilizing chemical vapordeposition (CVD) techniques such as, but not limited to, hot filamentand microwave plasma. In one embodiment, the microwave plasma chemicalvapor deposition (MPCVD) is utilized at low growth temperatures (i.e.,less than 450 degrees C.) such that high quality crystallinity may beattained while simultaneously maintaining integration with processedsubstrate materials where the substrate materials may be highlytemperature sensitive. Third step 1206 may form, for example, anintrinsic diamond layer 1304 (See FIG. 13).

The method 1200 may include a fourth step 1208 of forming semiconductordiamond layers. The fourth step 1208 may include fabrication steps suchas those steps described in regard to methods 100 and 400. Fourth step1208 may form, for example, a doped diamond layer 1302 (See FIG. 13).

The method 1200 may include a fifth step 1210 of forming semiconductordevices. The semiconductor devices may include, but are not limited todiodes, transistors, resistors, etc. The fifth step 1210 may includefabrication steps such as those steps described in regard to method 500.

FIG. 13 is a perspective view of a model of a doped diamond thin filmwafer 1300, such as may be fabricated by according to the method 1200for forming monolithically integrated circuits from diamondsemiconductor materials. The doped diamond thin film wafer 1300 mayinclude the doped diamond layer 1302, the intrinsic diamond layer 1304,and the substrate material layer 1306. Also shown is the layer boundary1308 and a layer boundary 1310.

A doped diamond thin film wafer fabricated according to the method 1200,such as doped diamond thin film wafer 1300, may provide beneficialthermal conductivity properties and crystal quality. For example, Ramanspectra data has shown that such a diamond signature peak at 1332 cm⁻¹may be substantially increased while disadvantageous graphiticconditions may be decreased around the G-Band at approximately 1575cm⁻¹. These advantageous features may permit new applicationcapabilities, such as passive diamond layers on processed silicon logicchips, in which high power heat elements may be monolithicallyintegrated with a heat spreading diamond material layer, such asintrinsic diamond layer 1304.

FIG. 14 shows a schematic diagram of a P⁺-i-N diode device 1400. AP⁺-i-N diode device, such as a P⁺-i-N diode device 1400, may befabricated, in part, according to method 1200. P⁺-i-N diode device 1400may include a lightly doped semiconductor region (i) 1404 between ap⁺-type semiconductor region 1408, and an n-type semiconductor region1402. FIG. 14 also shows a p-type semiconductor 1406 and a metalliccontact/bonding pad 1412 for connecting to the p⁺-type semiconductorregion 1408. The P⁺-i-N diode device 1400 components may be formed on asubstrate 1410 base.

Devices such as P⁺-i-N diode device 1400 may be employed in devices suchas, but not limited to, current controlled resistor applications such aspower attenuating and signal attenuation, as well in optoelectronicapplications such as sensors and LEDs where diamond materials may beused to form UV LED elements. In such LED devices, within a typical LEDvoltage operating range, both sufficient current density and currentlevels may be obtained conducive to device performance demands withdesired luminous efficacy. In addition, devices such as P⁺-i-N diodedevice 1400 may be utilized to form device driver elementsmonolithically formed on sapphire substrates, where the sapphire may beformed into LED elements thereby allowing a monolithically formed LEDwith driver on chip beneficial to higher temperature operatingenvironments.

FIG. 15 shows a block diagram of an embodiment of a method 1500 forforming monolithically integrated circuit devices from diamondsemiconductor materials. The steps provided in regard to method 1500 mayalso be employed, in part, to fabricate devices such as P⁺-i-N diodedevice 1400. The method 1500 may include a first step 1502 of depositingan aluminum pre-implant mask upon a diamond layer, for example, thediamond layer that may be formed after step 1208 of method 1200.

The method 1500 may include a second step 1504 of performing an implant.The method 1500 may include a third step 1506 of mask etching andannealing which may repair crystalline damage and activate thesemiconductor layer, for example, the doped diamond layer 1302. Theetching of method 1500 may be, for example, by the steps described inregard to method 900. The method 1500 may include a fourth step 1508 ofdepositing an aluminum pre-implant mask. The method 1500 may include afifth step 1510 of performing an implant. The method 1500 may include asixth step 1512 of mask etching and annealing which may again repaircrystalline damage. The method 1500 may include a seventh step 1514 ofdepositing an aluminum pre-implant mask. The method 1500 may include aneighth step 1516 of performing an implant. The method 1500 may include aninth step 1518 of mask etching and annealing which may again repaircrystalline damage. The method 1500 may include a tenth step 1520 inwhich the desired device may be further defined through lithography andfurther etching. The method 1500 may include a twelfth step 1522 inwhich the contacts are created, for example by the steps described inregard to methods 1000 and 1100.

FIG. 16 shows a schematic diagram of a NAND logic gate 1600 that may beformed, in part, by the methods disclosed herein. In NAND logic gate,signals 1602 and 1604 may be input into CMOS gate elements 1606 toproduce a logic output at 1608. In NAND logic gate 1600, the voltageand/or current may be dynamically controlled via monolithically formeddiamond element. For example, thin semiconductor diamond material may beformed via low temperature deposition on processed silicon deviceelements, where diamond semiconductor elements may be integrated in bothpassive and active circuit elements.

FIG. 17 shows a block diagram of an embodiment of a method 1700 forforming a transistor element, for example transistor element 1800 (seeFIG. 18), from diamond semiconductor materials. The first step of method1700 may be the same as the first step 1202 of method 1200, whichincludes selecting a substrate material, for example substrate material1306. The second step of method 1700 may be the same as the third step1206 of method 1200, which includes forming a diamond layer upon thesubstrate materials, for example, intrinsic diamond layer 1304. Themethod 1700 may include a third step 1702 of applying an acid clean andan implant mask. Third step 1702 may include applying cleaners known inthe art, such as Pirahna, such that dangling bonds may be substantiallyremoved and such that crystal smoothness is attained.

The fourth step of method 1700 may be the same as the fourth step 1208of method 1200, which includes fabricating layers within diamondmaterials. The method 1700 may include a fifth step 1704 of etching thediamond surface to again remove dangling bonds and improve crystalsmoothness. The method 1700 may include a sixth step 1706 of forming achannel, a source, a drain, and a gate region, for example throughfurther etching. In some embodiments, the channel may be include, forexample, graphene and CNT that may provide increased electron mobilityand improved electronic characteristics. The method 1700 may include aseventh step 1708 of forming contacts for the source and the drain. Themethod 1700 may include an eighth step 1710 of forming a gate dielectricregion. Dielectric materials may include aluminum oxide and polysiliconmaterials. The method 1700 may include a ninth step 1712 of forming agate metallic contact, for example aluminum gate contacts. In additionto transistors as described, the steps described in method 1700 may beused to form devices such as microwave devices, logic devices and powerconditioning devices, all of which may be formed monolithically usingdiamond semiconductor materials.

FIG. 18 is a model of a transistor 1800 that may be fabricator accordingto the method of FIG. 17. A transistor, such as transistor 1800, may befabricated, in part, according to method 1700. Transistor 1800 mayinclude an intrinsic diamond and substrate layer 1802, a channel layer1804, a source 1806, a drain 1808, a source contact 1810, and draincontact 1812, a gate dielectric 1814 and a gate contact 1816.

The word “exemplary” is used herein to mean “serving as an example,instance, or illustration.” Any embodiment or variant described hereinas “exemplary” is not necessarily to be construed as preferred oradvantageous over other embodiments or variants. All of the embodimentsand variants described in this description are exemplary embodiments andvariants provided to enable persons skilled in the art to make and usethe invention, and not necessarily to limit the scope of legalprotection afforded the appended claims.

The above description of the disclosed embodiments is provided to enableany person skilled in the art to make or use that which is defined bythe appended claims. The following claims are not intended to be limitedto the disclosed embodiments. Other embodiments and modifications willreadily occur to those of ordinary skill in the art in view of theseteachings. Therefore, the following claims are intended to cover allsuch embodiments and modifications when viewed in conjunction with theabove specification and accompanying drawings.

1. A method of fabricating a monolithically integrated diamondsemiconductor, the method including the steps of: seeding the surface ofa substrate material; forming a diamond layer upon the surface of thesubstrate material; and forming a semiconductor layer within the diamondlayer, wherein the diamond semiconductor of the semiconductor layer hasn-type donor atoms and a diamond lattice, wherein the n-type donor atomscontribute conduction electrons with mobility greater than 770 cm²/Vs tothe diamond lattice at 100 kPa and 300K, and wherein the n-type donoratoms are introduced to the lattice through ion tracks.
 2. The method offabricating a monolithically integrated diamond semiconductor of claim1, wherein the substrate material is selected from the group consistingof silicon, silicon oxide, refractory metal, glass, and wide band gapsemiconductor material.
 3. The method of fabricating a monolithicallyintegrated diamond semiconductor of claim 1, wherein the diamond layeris formed using chemical vapor deposition.
 4. The method of fabricatinga monolithically integrated diamond semiconductor of claim 1, whereinthe diamond layer is formed at or below 450 degrees Celsius.
 5. Amonolithically integrated diamond semiconductor device formed accordingto the method of claim
 1. 6. The monolithically integrated diamondsemiconductor device of claim 5, wherein the device is one of a groupconsisting of an LED, an attenuator, an amplifier, a switch, and asensor.
 7. The monolithically integrated diamond semiconductor device ofclaim 5, wherein the device includes logic elements.
 8. Themonolithically integrated diamond semiconductor device of claim 7,wherein the device is one of a group consisting of a transistor and adiode.
 9. (canceled)
 10. The method of fabricating a monolithicallyintegrated diamond semiconductor of claim 1, wherein the diamondsemiconductor of the semiconductor layer has a concentration between8×10¹⁷/cm³ and 2×10¹⁸/cm³ of the n-type donor atoms.